The present invention relates to low-power-CMOS integrated circuits, and to modules containing a low-power integrated circuit and a battery.
Battery-Backed ICs
Many system designs have begun to make use of the low standby power consumption of CMOS memory, to provide nonvolatile memory by attaching a very small battery. For example, many personal computers contain a battery-backed clock/calendar, which continues to keep time and date information when the computer is switched off. Many portable applications have also begun to use significant amounts of memory. In such applications, battery lifetime is one of the key performance parameters, from the end-user's point of view. If an integrated circuit which is sold for use in such systems turns out to consume more power than specified, so that the system batteries are exhausted early, this could be very unwelcome to the end-user. A further important class of applications is in packaging an integrated circuit, which includes some memory functions, together with a very small battery. The power supplied by the battery is used to preserve the data in memory while the system power supply is turned off. Thus, this arrangement permits the full advantages of nonvolatile memory to be achieved, without incurring the penalties of high-voltage circuitry and slow write time (as in EPROM or EEPROM floating-gate technology).
Power-Robbing
Various integrated circuits have extracted power from signal lines. For example, Pending PCT Application: Ser.No. PCT/U.S. 90/04286, Filed Jul. 30, 1990, which is hereby incorporated by reference, discloses a line-powered transceiver chip which robs power from an RS-232 line.
Integrated Circuit with Unique ID Number
PCT application PCT/U.S. 90/02891 (Publication No. WO 90/14626), which is hereby incorporated by reference, discloses a class of integrated circuits in which each has a fully unique serial number hard-wired into the chip.
Innovative Integrated Circuit
The disclosed inventions provide an integrated circuit, in which some areas of the chip are powered from battery, but other areas of the chip can draw power from one or more on-chip power-storage capacitors (which are diode-isolated to accumulate charge from an external signal line).
Use of Two Energy-Storage Capacitors
A particularly advantageous innovative teaching is the use of two energy-storage capacitors: one is connected to power the input buffer, and one is connected to power the logic which decodes the received signal.
Thus, the integrated circuit according to this class of embodiments includes at least three separate power domains: one powered by battery voltage; a second domain powered by energy stored in a large on-chip capacitor; and a third domain powered by energy stored in another on-chip capacitor.
The problem is that, as the voltage on the one-wire bus slowly slews down, it may pass through the high-current region (between V.sub.cap -V.sub.TP and V.sub.SS +V.sub.TN) in which both the NMOS and PMOS transistors of the input buffer are at least partially turned on. If this situation occurs (as it often may), the capacitor which is driving the input buffer will inevitably be drained. However, the use of two capacitors, in the presently preferred embodiment, avoids this problem. The signal line's input buffer draws power from one capacitor, and the decoder logic draws power from another. Thus, even if the first capacitor is depleted by the signal line's staying in the high-current regime, it will be powered up again when the signal line is again driven high; and the charge stored in the second capacitor will permit the decoding logic to operate. Preferably the second capacitor also powers circuitry which encodes a unique serial number for the chip. Thus, even after the battery has died, the chip can be interrogated to ascertain its unique serial number.